1. Field of the Invention
The present invention generally relates to a test key array on a wafer, and more particularly, to a test key array on a wafer for wafer acceptable test (hereinafter abbreviated as WAT).
2. Description of the Prior Art
In the standard semiconductor process, in order to evaluate the efficiency of each procedure and to confirm performance of the elements after the procedures, a WAT is performed on the wafers. The WAT includes an electrical test on the test pad structure disposed around the peripheral regions of the dice. And by analyzing the feedback signal, the stability of the semiconductor processes is confirmed as well as the characteristics and performance of each device of the dice.
Prior to the WAT, test keys are formed in the scribe lines around the dice. A device formed in a die is usually for logic computation or for memory, while a similar device is also formed in the scribe line as a part of the test key. The state-of-the-art also provides test pads electrically connected to the test keys. Accordingly, the test keys are electrically connected to an external circuit or probes of a probe card through the test pads to check the quality of the IC process in the WAT. After the WAT, a dicing process is performed to individualize each die on the wafer.
A dual damascene process is a method of forming a conductive wire coupled with a via plug in a dielectric layer. The dual damascene structure, comprising an upper wire and a lower via plug, is used to connect devices and wires in a semiconductor wafer and is insulated with other devices by the inter-layer dielectrics (ILD) around it. With the progress of the semiconductor fabrication and the miniaturization of the devices, size of the die and width of the scribe lines are consequently shrunk. Therefore, the dual damascene structure may make it easier to contact others devices or wires when some manufacturing defects occur, such as the over-etching defect or the misalignment defects. FIGS. 1A and 1B are schematic diagrams showing an over-etching issue happening in a dual damascene structure. As shown in FIG. 1, a via plug 1 is disposed in a dielectric layer 2, and electrically connected to a lower metal layer M1 and an upper metal layer M2, and especially connects the trace M1B of the lower metal layer M1, but does not contact the adjacent traces M1 or M1C directly. However, when an over-etching issue happens, as shown in FIG. 1B, the via plug 1 may contact the adjacent traces, and the issue mentioned above can happen more easily when the size of the die and width of the scribe lines are consequently shrunk.